Advanced Signal Integrity : Mastering High Speed Serial Data Technology by Ransom Stephens (PhD)

Mastering High Speed Serial Data
Technology
March 23rd – 24th, 2015
2-Day Advanced Class by Ransom Stephens, Ph.D. of 
Ransom’s Notes

A HIGHLY SPECIALISED CLASS

Ransom’s training teaches engineers how to master new concepts in signal
integrity, equalization and hardware debug. At multi-gigabit per second rate,
trouble comes in many forms and this course covers them all: signal distortion,
random jitters and noise at the transmitter etc. Using examples from cutting
edge serial technologies this intense two day course delivers a complete
technical understanding of potential trouble spots in high speed components
and systems, compliance, diagnostics and functional testing, and how the
standards attempt to insure interoperability.



Ransom Stephens
Dr. Ransom Stephens, Ph.D. is the author of over three hundred articles in the electronics industry, science journals and magazines on subjects ranging from the analysis of electrodynamics in high rate digital systems to fiber optics to quantum physics. As a research physicist and professor, he worked on experiments at universities and laboratories across the US and Europe making precise measurements of messy signals. After being awarded tenure, he shifted to private enterprise where his expertise in signal integrity analysis of electrical and fiber optic systems. Led to new jitter measurement techniques and methods for extracting signals from noise. He has served on the electrical working groups for several high data rate standards including PCIe and OIF CEI. Ransom is an entertaining teacher with a legendary reputation for delivering a clear understanding of complex topics.

ABOUT THE CLASS
Ransom’s training teaches engineers how to master new concepts in signal integrity, equalization and hardware debug. At multi-gigabit per seconds rate, trouble comes in many forms and this course covers them all: signal distortion, random jitters and noise at the transmitter; when or whether to switch from NRZ to PAM4 signaling, inter symbol interference and cross talk on circuit boards, backplanes and cables; and clock recovery, equalization, FEC and signal decoding at the receiver.

Using examples from cutting edge serial technologies – PCIe, OIF-CEI, sATA, Fiber Channel, 100 Gigabit Ethernet, -this intense two day course delivers a complete technical understanding of potential trouble spots in high speed components and systems, compliance, diagnostics and functional testing, and how the standards attempt to insure interoperability.

WHAT WILL YOU LEARN?
• Master high speed serial-data technologies
• Design functional, compliance, and manufacturing test systems
• Determine the sources of digital errors and how to correct them
• Master the dual-Dirac model, Q-scale, bathtub plots, and total jitter defined at a BER
• Understand the advantages and disadvantages of embedded and distributed clocks
• Know when to switch from NRZ to PAM4
• Identify the sources of RJ, DJ, DDJ, ISI, SJ, PJ, HPBJ, DCD, BUJ, E/OJ
• Devise transmitter pre/de-emphasis and receiver equalization schemes to improve BER
• Distinguish embedding and de-embedding and how effective they can be
• Appreciate the role of FEC and its limitations
• Understand emerging high data rate PHY specifications

WHO SHOULD ATTEND?
Research, design, manufacturing, system, and test engineers; digital and RF engineers; scientists, and university
students in electrical engineering and physics.



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click HERE to download registration form.
click HERE to register online.

Details

Duration 2 days
Member Fee RM 4,552.70
Non-Member Fee RM 4,764.70
PSMB Scheme SBL
SMECorp Funding -

Price is inclusive of 6% GST

Course Enquiry

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Schedule

Dates Venue
No scheduled classes